Acceptor: An element, such as boron, indium, and gallium used to create a free hole in a semiconductor. The acceptor atoms are required to have one less valence electron than the semiconductor.

Alignment Precision: Displacement of patterns that occurs during the photolithography process.

Anisotropic: A process of etching that has very little or no undercutting.

Area Contamination: Any foreign particles or material that are found on the surface of a wafer. This is viewed as discolored or smudged, and it is the result of stains, fingerprints, water spots, etc.

Azimuth, in Ellipsometry: The angle measured between the plane of incidence and the major axis of the ellipse.



Backside: The bottom surface of a silicon wafer. (Note: This term is not preferred; instead, use ‘back surface’.)

Base Silicon Layer: The silicon wafer that is located underneath the insulator layer, which supports the silicon film on top of the wafer.

Bipolar: Transistors that are able to use both holes and electrons as charge carriers.

Bonded Wafers: Two silicon wafers that have been bonded together by silicon dioxide, which acts as an insulating layer.

Bonding Interface: The area where the bonding of two wafers occurs.

Buried Layer: A path of low resistance for a current moving in a device. Many of these dopants are antimony and arsenic.

Buried Oxide Layer (BOX): The layer that insulates between the two wafers.



Carrier: Valence holes and conduction electrons that are capable of carrying a charge through a solid surface in a silicon wafer.

Chemical-Mechanical Polish (CMP): A process of flattening and polishing wafers that utilizes both chemical removal and mechanical buffing. It is used during the fabrication process.

Chuck Mark: A mark found on either surface of a wafer, caused by either a robotic end effector, a chuck, or a wand.

Cleavage Plane: A fracture plane that is preferred.

Crack: A mark found on a wafer that is greater than 0.25 mm in length.

Crater: Visible under diffused illumination, a surface imperfection on a wafer that can be distinguished individually.

Crosstalk: Unrelated circuits on a board interacting with one another. Ultimately causes device malfunction.

Conductivity (electrical): A measurement of how easily charge carriers can flow throughout a material.

Conductivity Type: The type of charge carriers in a wafer, such as “N-type” and “P-type”.

Contaminant, Particulate: (see light point defect)

Contamination Area: An area that contains particles that can negatively affect the characteristics of a silicon wafer.

Contamination Particulate: Particles found on the surface of a silicon wafer.

Crystal Defect: Parts of the crystal that contain vacancies and dislocations that can have an impact on a circuit’s electrical performance.

Crystal Indices: (see Miller indices)



Depletion Layer: A region on a wafer that contains an electrical field that sweeps out charge carriers.

Dimple: A concave depression found on the surface of a wafer that is visible to the eye under the correct lighting conditions.

Donor: A contaminate that has donated extra “free” electrons, thus making a wafer “N-Type”.

Dopant: An element that contributes an electron or a hole to the conduction process, thus altering the conductivity. Dopants for silicon wafers are found in Groups III and V of the Periodic Table of the Elements.

Doping: The process of the donation of an electron or hole to the conduction process by a dopant.



Edge Chip and Indent: An edge imperfection that is greater than 0.25 mm.

Edge Exclusion Area: The area located between the fixed quality area and the periphery of a wafer. (This varies according to the dimensions of the wafer.)

Edge Exclusion, Nominal (EE): The distance between the fixed quality area and the periphery of a wafer.

Edge Profile: The edges of two bonded wafers that have been shaped either chemically or mechanically.

Etch: A process of chemical reactions or physical removal to rid the wafer of excess materials.



Fixed Quality Area (FQA): The area that is most central on a wafer surface.

Flat: A section of the perimeter of a wafer that has been removed for wafer orientation purposes.

Flat Diameter: The measurement from the center of the flat through the center of the wafer to the opposite edge of the wafer. (Perpendicular to the flat)

Four-Point Probe: Test equipment used to test resistivity of wafers.

Furnace and Thermal Processes: Equipment with a temperature gauge used for processing wafers. A constant temperature is required for the process.

Front Side: The top side of a silicon wafer. (This term is not preferred; use front surface instead.)



Goniometer: An instrument used in measuring angles.

Gradient, Resistivity: (not preferred; see resistivity variation)

Groove: A scratch that was not completely polished out.



Hand Scribe Mark: A marking that is hand scratched onto the back surface of a wafer for identification purposes.

Haze: A mass concentration of surface imperfections, often giving a hazy appearance to the wafer.

Hole: Similar to a positive charge, this is caused by the absence of a valence electron.



Ingot: A cylindrical solid made of polycrystalline or single crystal silicon from which wafers are cut.


Laser Light-Scattering Event: A signal pulse that locates surface imperfections on a wafer.

Lay: The main direction of surface texture on a wafer.

Light Point Defect (LPD): (Not preferred; see localized light-scatterer)

Lithography: The process used to transfer patterns onto wafers.

Localized Light-Scatterer: One feature on the surface of a wafer, such as a pit or a scratch that scatters light. It is also called a light point defect.

Lot: Wafers of similar sizes and characteristics placed together in a shipment.



Majority Carrier: A carrier, either a hole or an electron that is dominant in a specific region, such as electrons in an N-Type area.

Mechanical Test Wafer: A silicon wafer used for testing purposes.

Microroughness: Surface roughness with spacing between the impurities with a measurement of less than 100 μm.

Miller Indices, of a Crystallographic Plane: A system that utilizes three numbers to identify plan orientation in a crystal.

Minimal Conditions or Dimensions: The allowable conditions for determining whether or not a wafer is considered acceptable.

Minority Carrier: A carrier, either a hole or an electron that is not dominant in a specific region, such as electrons in a P-Type area.

Mound : A raised defect on the surface of a wafer measuring more than 0.25 mm.



Notch: An indent on the edge of a wafer used for orientation purposes.



Orange Peel: A roughened surface that is visible to the unaided eye.



Particle: A small piece of material found on a wafer that is not connected with it.

Particle Counting: Wafers that are used to test tools for particle contamination.

Particulate Contamination: Particles found on the surface of a wafer. They appear as bright points when a collineated light is shined on the wafer.

Pit: A non-removable imperfection found on the surface of a wafer.

Point Defect: A crystal defect that is an impurity, such as a lattice vacancy or an interstitial atom.

Premium Wafer: A wafer that can be used for particle counting, measuring pattern resolution in the photolithography process, and metal contamination monitoring. This wafer has very strict specifications for a specific usage, but looser specifications than the prime wafer.

Primary Orientation Flat: The longest flat found on the wafer.

Process Test Wafer: A wafer that can be used for processes as well as area cleanliness.

Profilometer: A tool that is used for measuring surface topography.


Resistivity (Electrical) : The amount of difficulty that charged carriers have in moving throughout material.

Required: The minimum specifications needed by the customer when ordering wafers.

Roughness: The texture found on the surface of the wafer that is spaced very closely together.



Saw Marks: Surface irregularities

Scan Direction: In the flatness calculation, the direction of the subsites.

Scratch: A mark that is found on the wafer surface.

Secondary Flat: A flat that is smaller than the primary orientation flat. The position of this flat determines what type the wafer is, and also the orientation of the wafer.

Site: An area on the front surface of the wafer that has sides parallel and perpendicular to the primary orientation flat. (This area is rectangular in shape)

Site Array: a neighboring set of sites

Slip: A defect pattern of small ridges found on the surface of the wafer.

Smudge: A defect or contamination found on the wafer caused by fingerprints.

Striation: Defects or contaminants found in the shape of a helix.

Subsite, of a Site: An area found within the site, also rectangular. The center of the subsite must be located within the original site.

Surface Texture: Variations found on the real surface of the wafer that deviate from the reference surface.



Test Wafer: A silicon wafer that is used in manufacturing for monitoring and testing purposes.

Thickness of Top Silicon Film: The distance found between the face of the top silicon film and the surface of the oxide layer.

Top Silicon Film: The layer of silicon on which semiconductor devices are placed. This is located on top of the insulating layer.

Total Indicator Reading (TIR): The smallest distance between planes on the surface of the wafer.



Virgin Test Wafer: A wafer that has not been used in manufacturing or other processes.

Void: The lack of any sort of bond (particularly a chemical bond) at the site of bonding.



Waves: Curves and contours found on the surface of the wafer that can be seen by the naked eye.

Waviness: Widely spaced imperfections on the surface of a wafer.


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