Silicon on insulator wafers are most common in microelectromechanical systems (MEMS) and advanced complementary metal–oxide–semiconductor (CMOS) integrated circuit fabrications. Silicon on insulator wafers improve many of the processes that more traditional silicon wafers are used in.

These wafers provide a manufacturing solution which helps reduce power and heat while increasing the speed performance of a device. Silicon on insulator wafers are a three layer material stack composed of the following: an active layer of prime quality silicon (device layer), a buried oxide layer (box) of electrically insulating silicon dioxide, and a bulk silicon support wafer (handle). SOI wafers are unique products for specific end-user applications.

SOI Fabrication Processes

There are 3 primary ways to fabricate silicon on insulator wafers, and each one produces a substrate with slightly different film properties. A member of the SVM sales team will determine which fabrication method is best for your project’s requirements when you submit your requirements through our contact form or via email.

Bonded & Etchback SOI (BESOI)

Some applications favor this method because there is no implantation, which minimizes damage done to the substrate surface. There are also few free charge carriers, which can improve the long term performance of a device. Due to the nature of CMP and wafer grinding processes, this is generally used to manufacture SOI wafers with a device layer >2μm.

SVM can manufacture these wafers in any diameter from 76mm to 200mm.

Separation by Implantation of Oxygen (SIMOX)

This process is often preferred to other fabrication techniques for silicon on insulator wafers because of its ability to precisely control the thickness of the oxide layer. While it is rare, some applications replace oxygen with nitrogen or oxynitride without adverse affects, although the vast majority of applications require oxygen. This is a highly versatile manufacturing technique that can produce device layers >.5um, which means it covers a majority of thin film SOI wafers, as well as thick film SOI.

SmartCut®

This method combines the repeatability of SIMOX with the flexibility of BESOI, allowing different oxide film thicknesses while maintaining a high uniformity across different wafers. In contrast to BESOI, the bonded wafer can be recycled, which makes this method slightly more cost effective. Due to the cleaving process of thin film SOI wafers, this method can produce device layers as thin as 50nm (500Å, 0.05μm). This method is only available on 200mm wafers, because there is advanced tooling required to produce such thin device layers. In most circumstances, we can downsize these wafers to make 100mm or 150mm wafers for an additional cost, with the risk of some yield loss (Average yield is ~90-95%, but can vary).

Item

Minimum Spec

Maximum Spec

Device Layer
Crystal Growth Method CZ, FZ -
Crystal Orientation<1-0-0>±0.5°, <1-1-0>±0.5°, <1-1-1>±0.5°-
Type/DopantP/Boron, N/Phos, Intrinsic-
Resistivity0.001 ohm-cm>1000 ohm-cm
Diameter50.8mm ± 0.5mm200mm ± 0.5mm
Thickness>1.5μm200μm
Front SurfacePolished-
Na, Al, Cr, Fe, Ni, Cu, Zn, Ca≤5e10 -
LPD (Size > 0.3µm)≤20 -
Edge Chip, ScratchNone-
Surface Roughness (nm)≤0.4nm -
Buried Oxide - BOX Layer (edge exclusion is 5mm unless noted otherwise)
Thickness0.050μm5μm
Handle Substrate (edge exclusion is 5mm unless noted otherwise)
Crystal Growth MethodCZ, FZ -
Crystal Orientation<1-0-0>±0.5, <1-1-0>±0.5, <1-1-1>±0.5 -
Type/DopantP/Boron, N/Phos, Intrinsic -
Resistivity 0.001 ohm-cm>1000 ohm-cm
Back SurfaceEtched or Polished with/without Oxide-
Diameter50.8mm ± 0.5mm 200mm ± 0.5mm
Overall Wafer Characteristics
TTV (Best)≤2μm -
Warp (Best)≤30μm -
Bow (Best)≤30μm -
Thickness300 ± 2μm (flexible) 725 ± 25μm

Item

Minimum Spec

Maximum Spec

Device Layer
Crystal Growth MethodCZ, FZ-
Crystal Orientation<1-0-0>±0.5-
Type/DopantP/Boron-
Resistivity>1 ohm-cm>1000 ohm-cm
Diameter150mm ± 0.5mm200mm ± 0.5mm
Thickness50nm1nm
Front SurfacePolished-
Na, Al, Cr, Fe, Ni, Cu, Zn, Ca≤5e10 -
LPD (Size > 0.2 µm)≤50-
Edge Chip, ScratchNone-
Surface Roughness (nm)≤0.4nm -
Buried Oxide - BOX Layer (edge exclusion is 5mm unless noted otherwise)
Thickness0.050μm3μm
Handle Substrate (edge exclusion is 5mm unless noted otherwise)
Crystal Growth MethodCZ, FZ-
Crystal Orientation<1-0-0>±0.5-
Type/DopantP/Boron -
Resistivity>1 ohm-cm>1000 ohm-cm
Back SurfaceEtched or Polished with/without Oxide -
Diameter150mm ± 0.5mm 200mm ± 0.5mm
Overall Wafer Characteristics
TTV (Best)≤5μm -
Warp (Best)≤60μm -
Bow (Best)≤60μm -
Thickness675±25μm 725±25μm

*If your requirements are outside of the above specifications, please contact us to discuss further. For different device layer thicknesses and custom SOI wafers, there may be a minimum order quantity of 15-25 wafers for certain specifications.

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