Cavity SOI

Cavity silicon-on-insulator (C-SOI) wafers are a cutting edge SOI technology where the handle wafer contains pre-etched cavities. The cavities, sometimes called patterns, are bonded facing inward resulting in buried cavities inside the wafers. These have many applications in microelectromechanical system (MEMS) technology and offer many advantages over bulk silicon micro-machining, as well as traditional SOI technology. One major advantage of this technology is decreased parasitic capacitance between the device and handle layer of the SOI wafer. This will allow for devices to function much more efficiently. Using deeper cavities and smaller bonding areas can lessen parasitic capacitance further, as long as other variables are controlled.

If you are interested in purchasing C-SOI from SVM, please contact us to get a copy of our cavity layer design rules.

C-SOI Fabrication Process:

Cavity SOI fabrication differs slightly from more conventional SOI fabrication, as the formation of cavities leads to different advantages and potential shortcomings. This process has primarily been optimized for use in the MEMS industry, although it has the potential to improve device function in a range of applications.

In some instances, pillars are etched into the cavities to improve total thickness variance (TTV) and device function. Including pillars creates higher quality silicon diaphragms (the layer of silicon over cavity) and improves cavity uniformity, while higher aspect ratios will improve device performance and improve process control during lithography. Since the size of cavities changes the ability to thin the device layer, including pillars can influence the TTV and integrity of the wafers. If these aren’t clearly defined, it can affect resonance properties causing different regions of the substrate to vibrate at different amplitudes, which can lead to very high TTV, device malfunction, and breakage.

Step by Step Process Flow:

1. Prep bare silicon substrate

• Fabrication begins with a cleaning to remove any surface particles that may create issues during fabrication.

2. Apply a photomask to the handle substrate to clearly define cavities that will be etched into the wafer

• To create the pattern, a plasma polymer film is applied to the substrate. In this step, pillars are also defined if they will be used. For many projects, the use of pillars will allow for deeper cavities and higher aspect ratios, while limiting the risk of notching and other issues that may arise during etching or secondary processing.

3. Deep reactive ion etching (DRIE) removes material to create cavities, followed by a photoresist strip

• DRIE etching removes very precise amounts of silicon to create cavities defined by the photomask. Areas not covered by the photomask are etched via ion bombardment to create the desired cavities. During this step, support pillars are cut into the cavities. DRIE is most common because of its high etch rate uniformity and overall simplicity. Since this requires liquid etchants, this process will continue to optimize as the technology develops.
• The etch rate varies from 0.8 μm/min to 1.25 μm/min depending on the width and aspect ratio of the cavities.  After etching cavities, the photomask is stripped, leaving a patterned wafer.

4. Clean substrate

• After etching the wafer, it is important to remove any excess silicon and photoresist that may remain. This will prevent issues during bonding.

5. Insulating layer deposition

• Thermal oxide (or an alternative insulator) can be deposited before or after etching, and in some cases both depending on the project’s requirements. If oxide deposition is done prior to etching, then etching will go through the oxide layer down to the substrate; etching may remove some of the underlying substrate as well. This may result in cavity walls that are bare of any insulator, depending on the depth.
• When oxide layers grow after etching, small bumps will form on the corners of the cavity. The bumps range from 5-20 μm in height, varying with the thickness of the insulating film. This will also result in a slight rounding of all corners due to the nature of silicon dioxide formation.

6. Bonded with cap wafer (device layer of SOI wafer)

• For best outcomes, CSOI wafers bond directly in a vacuum. These wafers are bonded with water or a similarly neutral material, then annealed at 1100°C for up to 2 hours to solidify the bond. After annealing, there is no adhesive facilitating the bond between wafers. Performing this in a vacuum helps prevent the cavities from holding excess air and other contaminants. This also helps maintain consistency when thinning the cap wafer because pressure inside the cavities will be uniform across the entire substrate.

7. Thin the top (device) wafer with CMP/KOH (potassium hydroxide) etching

• The cap wafer must be thinned to the desired device layer thickness. This is the most variable step in CSOI fabrication, because the thinning rate and quality relies heavily on the quality of the bond, as well as the physical characteristics of the cavities. Naturally the silicon diaphragms will vibrate during this stage, creating a variable TTV over these regions. Performing previous fabrication steps inside a vacuum helps prevent many of these issues that may arise.

8. Secondary processing, depending on application and device specification

• In contrast to more conventional SOI, CSOI wafers can undergo secondary back side processing after fabrication. This means extremely thin membranes, delicate surface structures, metal film stacks, and generally more design freedom than conventional SOI wafers.

Advantages of C-SOI Wafers:

• Reduces device cost without compromising precision or quality.
• Reduces device size. The inclusion of cavities makes extremely thin handle/BOX/device layers possible.
• Bonding patterned wafers enables double-side processing of the SOI layer and opens up many possibilities in the field of micromechanics.

Applications:

Pre-etched SOI wafers are a suitable platform for vertically and horizontally moving structures in various applications, such as capacitive inertial sensors, pressure sensors, microphones, and microfluidic devices.

While most of the uses are currently within MEMS and sensor applications, these wafers can improve any SOI wafer application.